library IEEE;
use IEEE.STD_LOGIC_1164.ALL,IEEE.Numeric_std.ALL;

entity pdedff is
generic(
        impl_rn                                 : integer:=1;                           -- async reset available if 1
        impl_sn                                 : integer:=1 );                         -- async   set available if 1
port(
        rn                                      : in  std_ulogic;
        sn                                      : in  std_ulogic;
        d                                       : in  std_ulogic;
        c                                       : in  std_ulogic;
        q                                       : out std_ulogic );
end pdedff;

-- pseudo dual-edge D-flipflop
-- reset and set are low active and can be (de)activated using the generic paramters

architecture behavior of pdedff is

signal          ff_rise,ff_fall                 : std_ulogic;

begin

process(rn,sn,c)
begin
if (impl_rn=1 AND rn='0') then
        ff_rise<='0';
elsif (impl_sn=1 AND sn='0') then
        ff_rise<='1';
elsif rising_edge(c) then
        if (d='1') then
                ff_rise<=NOT(ff_fall);
        else    ff_rise<=ff_fall;
        end if;
end if;
end process;

process(rn,sn,c)
begin
if (impl_rn=1 AND rn='0') then
        ff_fall<='0';
elsif (impl_sn=1 AND sn='0') then
        ff_fall<='0';
elsif falling_edge(c) then
        if (d='1') then
                ff_fall<=NOT(ff_rise);
        else    ff_fall<=ff_rise;
        end if;
end if;
end process;

q <= '0' when (impl_rn=1 AND rn='0') else
     '1' when (impl_sn=1 AND sn='0') else
     ff_rise XOR ff_fall;
     -- rn and sn used to suppress spikes

end behavior;